1. Field of the Invention
This invention relates to a phase locked loop (PLL) circuit, and more particularly to a PLL circuit applied with an input signal which would often cause discontinuous changes in phase.
2. Description of the Prior Art
A digital signal processing circuit such as a timebase collector (TBC) in a video tape recorder (VTR) uses a memory for temporarily storing a digital video signal as shown in FIG. 1. Referring to FIG. 1, a digital video signal is written into a memory 51 in response to a write clock and the stored digital video signal is read out from the memory 51 in response to a read clock. The address of the memory 51 is reset periodically, for example at intervals of horizontal scanning period (H), by a reset signal. Used as the reset signal is a reference signal d which is a periodic pulse train as shown in FIG. 2 produced from the horizontal synchronizing signal or the burst signal of the video signal reproduced via a pair of rotary heads from a recording tape. The write clock is generated from the reference signal by a PLL circuit 50 comprising a phase comparator 2, a low-pass filter (LPF) 3, a voltage controlled oscillator (VCO) 4 and a frequency divider 5. The PLL circuit 50 operates so that the phase of the output signal e of the frequency divider 5 is locked to the phase of the reference signal d. The response speed of the PLL circuit 50 which is determined by the time constant of the LPF 3 cannot be made too short so that the PLL circuit 50 does not respond to a noise.
The PLL circuit 50 arranged as above cannot immediately recover the stable state when the reference signal d causes a discontinuous change in phase. Since the video signal recorded on the recorded tape is reproduced via a pair of alternately switched heads, there would be caused a discontinuity of the reproduced signal, resulting in a sudden change of the phase of the reference signal. Referring to FIG. 2, HSW is the head switching signal for periodically changing over the pair of heads, and the reference signal causes a discontinuous phase change between pulses d.sub.1 and d.sub.2. The phase comparator 2 generates an error signal g corresponding to the phase difference between the reference signal d and the output signal e of the frequency divider 5. The frequency divider 5 resets itself by the reset signal f synchronized with the signal e. Due to the time constant of the LPF 3, the error signal g is converted by the LPF 3 to a gradually changing voltage signal h. Therefore, it takes a fairly long time (about 10H in the case of FIG. 2) for the PLL circuit 50 to recover the stable state in which the phase of the output signal of the frequency divider 5 is locked to the phase of the reference signal after the discontinuous phase change.